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4a65e0986e
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| 4a65e0986e |
130
parallel.c
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130
parallel.c
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#include "parallel.h"
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#include "io.h"
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#include "irq.h"
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#include "serial.h" // or your print/terminal for debug
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// Standard PC LPT base addresses
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static const uint16_t lpt_base_addrs[LPT_MAX_PORTS] = {
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0x378, // LPT1
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0x278 // LPT2
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};
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lpt_device_t lpt_devices[LPT_MAX_PORTS];
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// Register offsets
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#define LPT_DATA(base) (base + 0)
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#define LPT_STATUS(base) (base + 1)
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#define LPT_CONTROL(base) (base + 2)
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// STATUS bits
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// bit 7: Busy (inverted), 6: Ack, 5: Paper Out, 4: Select, 3: Error
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// CONTROL bits
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// bit 0: Strobe, 1: Auto Linefeed, 2: Init, 3: Select In, 5: Bidirectional (PS/2)
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// Simple presence check: write/read control & status
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static bool lpt_detect(uint16_t base) {
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uint8_t orig_ctrl = inb(LPT_CONTROL(base));
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outb(LPT_CONTROL(base), orig_ctrl ^ 0x0F);
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uint8_t new_ctrl = inb(LPT_CONTROL(base));
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outb(LPT_CONTROL(base), orig_ctrl);
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// If bits changed as expected, port likely exists
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if (((orig_ctrl ^ new_ctrl) & 0x0F) == 0x0F) {
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return true;
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}
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return false;
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}
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static void lpt_configure_bidir(uint16_t base, bool enable) {
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uint8_t ctrl = inb(LPT_CONTROL(base));
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if (enable) {
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ctrl |= (1 << 5); // Set bidirectional bit (PS/2)
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} else {
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ctrl &= ~(1 << 5);
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}
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outb(LPT_CONTROL(base), ctrl);
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}
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void lpt_set_mode(lpt_port_t port, lpt_mode_t mode) {
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if (port < 0 || port >= LPT_MAX_PORTS) return;
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if (!lpt_devices[port].present) return;
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uint16_t base = lpt_devices[port].base;
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switch (mode) {
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case LPT_MODE_COMPAT:
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lpt_configure_bidir(base, false);
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break;
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case LPT_MODE_BIDIR:
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lpt_configure_bidir(base, true);
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break;
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case LPT_MODE_EPP:
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// TODO: EPP requires chipset support & config
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// For now, just enable bidir as a baseline
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lpt_configure_bidir(base, true);
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break;
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case LPT_MODE_ECP:
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// TODO: ECP requires FIFO, DMA, and ECR register
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// Stub for future implementation
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lpt_configure_bidir(base, true);
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break;
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}
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lpt_devices[port].mode = mode;
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}
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void lpt_write_byte(lpt_port_t port, uint8_t value) {
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if (port < 0 || port >= LPT_MAX_PORTS) return;
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if (!lpt_devices[port].present) return;
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uint16_t base = lpt_devices[port].base;
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// Wait until not busy (bit 7 is inverted busy)
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while (!(inb(LPT_STATUS(base)) & 0x80))
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;
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outb(LPT_DATA(base), value);
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// Pulse strobe
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uint8_t ctrl = inb(LPT_CONTROL(base));
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outb(LPT_CONTROL(base), ctrl | 0x01);
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outb(LPT_CONTROL(base), ctrl & ~0x01);
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}
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uint8_t lpt_read_byte(lpt_port_t port) {
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if (port < 0 || port >= LPT_MAX_PORTS) return 0xFF;
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if (!lpt_devices[port].present) return 0xFF;
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uint16_t base = lpt_devices[port].base;
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// In bidirectional mode, data register is input
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return inb(LPT_DATA(base));
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}
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// IRQ hook: you wire this into your IRQ handler for the LPT IRQ (usually 7 or 5)
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void lpt_irq_handler(lpt_port_t port) {
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// For now, just a stub. Later:
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// - read status
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// - acknowledge interrupt
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// - wake waiting writer/reader
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(void)port;
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}
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// Initialize all LPT ports
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void lpt_init_all(void) {
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for (int i = 0; i < LPT_MAX_PORTS; i++) {
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lpt_devices[i].base = lpt_base_addrs[i];
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lpt_devices[i].present = lpt_detect(lpt_devices[i].base);
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lpt_devices[i].mode = LPT_MODE_COMPAT;
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lpt_devices[i].irq = 0; // You can fill this if you parse BIOS/PCI/ACPI
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if (lpt_devices[i].present) {
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serial_write("LPT detected at base 0x");
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// use your print_hex here if you want
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}
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}
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// If you want interrupt-driven I/O:
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// - Map LPT IRQ (usually 7 for LPT1, 5 for LPT2) in your PIC/IRQ layer
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// - In your IRQ handler, call lpt_irq_handler(port)
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}
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