Create pci.h

kernel/pci.h

@@ -0,0 +1,60 @@
+#ifndef PCI_H
+#define PCI_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/* I/O Ports for PCI Configuration Mechanism #1 */
+#define PCI_CONFIG_ADDRESS 0xCF8
+#define PCI_CONFIG_DATA    0xCFC
+
+/* Common PCI Configuration Register Offsets */
+#define PCI_REG_VENDOR_ID       0x00
+#define PCI_REG_DEVICE_ID       0x02
+#define PCI_REG_COMMAND         0x04
+#define PCI_REG_STATUS          0x06
+#define PCI_REG_REVISION_ID     0x08
+#define PCI_REG_PROG_IF         0x09
+#define PCI_REG_SUBCLASS        0x0A
+#define PCI_REG_CLASS           0x0B
+#define PCI_REG_CACHE_LINE_SIZE 0x0C
+#define PCI_REG_LATENCY_TIMER   0x0D
+#define PCI_REG_HEADER_TYPE     0x0E
+#define PCI_REG_BIST            0x0F
+#define PCI_REG_BAR0            0x10
+#define PCI_REG_BAR1            0x14
+#define PCI_REG_BAR2            0x18
+#define PCI_REG_BAR3            0x1C
+#define PCI_REG_BAR4            0x20
+#define PCI_REG_BAR5            0x24
+#define PCI_REG_INTERRUPT_LINE  0x3C
+
+typedef struct {
+    uint32_t base_address;
+    uint32_t size;
+    bool     is_io;
+    bool     is_prefetchable; // Only for Memory BARs
+} pci_bar_t;
+
+typedef struct {
+    uint8_t  bus;
+    uint8_t  device;
+    uint8_t  function;
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint8_t  class_code;
+    uint8_t  subclass;
+    uint8_t  interrupt_line;
+} pci_dev_t;
+
+/* Function Prototypes */
+uint32_t pci_config_read_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+void     pci_config_write_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t data);
+
+uint16_t pci_config_read_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+uint8_t  pci_config_read_byte(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+
+pci_bar_t pci_get_bar(uint8_t bus, uint8_t slot, uint8_t func, uint8_t bar_index);
+void      pci_init(void);
+
+#endif