diff --git a/kernel/pci.c b/kernel/pci.c new file mode 100644 index 0000000..14d6c2d --- /dev/null +++ b/kernel/pci.c @@ -0,0 +1,109 @@ +#include "pci.h" +#include "io.h" + +/* --- Configuration Access Functions --- */ + +uint32_t pci_config_read_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) { + uint32_t address = (uint32_t)((uint32_t)1 << 31) | + ((uint32_t)bus << 16) | + ((uint32_t)slot << 11) | + ((uint32_t)func << 8) | + (offset & 0xFC); + outl(PCI_CONFIG_ADDRESS, address); + return inl(PCI_CONFIG_DATA); +} + +void pci_config_write_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t data) { + uint32_t address = (uint32_t)((uint32_t)1 << 31) | + ((uint32_t)bus << 16) | + ((uint32_t)slot << 11) | + ((uint32_t)func << 8) | + (offset & 0xFC); + outl(PCI_CONFIG_ADDRESS, address); + outl(PCI_CONFIG_DATA, data); +} + +/* To read a word or byte, we read the Dword and shift/mask */ +uint16_t pci_config_read_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) { + uint32_t dword = pci_config_read_dword(bus, slot, func, offset); + return (uint16_t)((dword >> ((offset & 2) * 8)) & 0xFFFF); +} + +uint8_t pci_config_read_byte(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset) { + uint32_t dword = pci_config_read_dword(bus, slot, func, offset); + return (uint8_t)((dword >> ((offset & 3) * 8)) & 0xFF); +} + +/* --- BAR Decoding Logic --- */ + +pci_bar_t pci_get_bar(uint8_t bus, uint8_t slot, uint8_t func, uint8_t bar_index) { + pci_bar_t bar = {0}; + uint8_t offset = PCI_REG_BAR0 + (bar_index * 4); + + uint32_t initial_val = pci_config_read_dword(bus, slot, func, offset); + + // The Size Masking Trick + pci_config_write_dword(bus, slot, func, offset, 0xFFFFFFFF); + uint32_t mask = pci_config_read_dword(bus, slot, func, offset); + pci_config_write_dword(bus, slot, func, offset, initial_val); // Restore + + if (initial_val & 0x1) { + // I/O Space BAR + bar.is_io = true; + bar.base_address = initial_val & 0xFFFFFFFC; + bar.size = ~(mask & 0xFFFFFFFC) + 1; + } else { + // Memory Space BAR + bar.is_io = false; + bar.base_address = initial_val & 0xFFFFFFF0; + bar.is_prefetchable = (initial_val & 0x8) != 0; + bar.size = ~(mask & 0xFFFFFFF0) + 1; + } + + return bar; +} + +/* --- Enumeration and Discovery --- */ + +void pci_check_function(uint8_t bus, uint8_t slot, uint8_t func) { + uint16_t vendor_id = pci_config_read_word(bus, slot, func, PCI_REG_VENDOR_ID); + if (vendor_id == 0xFFFF) return; + + uint16_t device_id = pci_config_read_word(bus, slot, func, PCI_REG_DEVICE_ID); + uint8_t class_code = pci_config_read_byte(bus, slot, func, PCI_REG_CLASS); + + /* Optional: Set Master Latency Timer if it is 0. + A value of 32 (0x20) or 64 (0x40) is typical. + */ + uint8_t latency = pci_config_read_byte(bus, slot, func, PCI_REG_LATENCY_TIMER); + if (latency == 0) { + // pci_config_write_byte would be needed here, or write a dword with the byte modified + uint32_t reg_0c = pci_config_read_dword(bus, slot, func, 0x0C); + reg_0c |= (0x20 << 8); // Set latency to 32 + pci_config_write_dword(bus, slot, func, 0x0C, reg_0c); + } + + // Replace with your kernel's print/logging function + // printf("Found PCI Device: %x:%x Class: %x at %d:%d:%d\n", vendor_id, device_id, class_code, bus, slot, func); +} + +void pci_init(void) { + for (uint16_t bus = 0; bus < 256; bus++) { + for (uint8_t slot = 0; slot < 32; slot++) { + // Check Function 0 first + uint16_t vendor = pci_config_read_word(bus, slot, 0, PCI_REG_VENDOR_ID); + if (vendor == 0xFFFF) continue; + + pci_check_function(bus, slot, 0); + + // Check if this is a multi-function device + uint8_t header_type = pci_config_read_byte(bus, slot, 0, PCI_REG_HEADER_TYPE); + if (header_type & 0x80) { + // Check functions 1-7 + for (uint8_t func = 1; func < 8; func++) { + pci_check_function(bus, slot, func); + } + } + } + } +} diff --git a/kernel/pci.h b/kernel/pci.h new file mode 100644 index 0000000..8f1e0c3 --- /dev/null +++ b/kernel/pci.h @@ -0,0 +1,60 @@ +#ifndef PCI_H +#define PCI_H + +#include +#include + +/* I/O Ports for PCI Configuration Mechanism #1 */ +#define PCI_CONFIG_ADDRESS 0xCF8 +#define PCI_CONFIG_DATA 0xCFC + +/* Common PCI Configuration Register Offsets */ +#define PCI_REG_VENDOR_ID 0x00 +#define PCI_REG_DEVICE_ID 0x02 +#define PCI_REG_COMMAND 0x04 +#define PCI_REG_STATUS 0x06 +#define PCI_REG_REVISION_ID 0x08 +#define PCI_REG_PROG_IF 0x09 +#define PCI_REG_SUBCLASS 0x0A +#define PCI_REG_CLASS 0x0B +#define PCI_REG_CACHE_LINE_SIZE 0x0C +#define PCI_REG_LATENCY_TIMER 0x0D +#define PCI_REG_HEADER_TYPE 0x0E +#define PCI_REG_BIST 0x0F +#define PCI_REG_BAR0 0x10 +#define PCI_REG_BAR1 0x14 +#define PCI_REG_BAR2 0x18 +#define PCI_REG_BAR3 0x1C +#define PCI_REG_BAR4 0x20 +#define PCI_REG_BAR5 0x24 +#define PCI_REG_INTERRUPT_LINE 0x3C + +typedef struct { + uint32_t base_address; + uint32_t size; + bool is_io; + bool is_prefetchable; // Only for Memory BARs +} pci_bar_t; + +typedef struct { + uint8_t bus; + uint8_t device; + uint8_t function; + uint16_t vendor_id; + uint16_t device_id; + uint8_t class_code; + uint8_t subclass; + uint8_t interrupt_line; +} pci_dev_t; + +/* Function Prototypes */ +uint32_t pci_config_read_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset); +void pci_config_write_dword(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset, uint32_t data); + +uint16_t pci_config_read_word(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset); +uint8_t pci_config_read_byte(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset); + +pci_bar_t pci_get_bar(uint8_t bus, uint8_t slot, uint8_t func, uint8_t bar_index); +void pci_init(void); + +#endif